This invention relates to the field of semiconductor manufacture, and more particularly to a floating gate memory device having a container structure for storing an electric charge.
As with most electronic devices, an engineering design goal for programmable read-only memories (PROMs) is to decrease the size and power consumption of the devices. Power consumption includes the power used to program PROMs as well as operating power. Decreasing the cell size of a PROM device also decreases the time required to output the desired information from a selected floating gate.
Shrinking a PROM such as an erasable device (EPROM) includes narrowing the width of the floating gate and the control gate with a similar reduction in the width of the channel. Narrowing the width of the two gates, however, decreases the coupling capacitance between the two gates which increases the likelihood of errors while reading the cell charge.
The floating gate of an EPROM forms a capacitor with the control gate and also with the source, the drain, and the channel of the cell. If the surface areas of the floating and/or control gates are increased, the gate width can be reduced while maintaining the same coupling capacitance between the gates. The coupling capacitances associated with the floating gate are described by the coupling coefficient, which is depicted by the equation
CC=C1/(C1+C2+C3+C4)
where CC is the coupling coefficient and C1, C2, C3, and C4 represent the capacitance between the floating gate and the control gate, the source, the drain, and the channel respectively. As an example, if C1=0.5, C2=0.1, C3=0.1, and C4=0.3, the coupling coefficient would equal 0.5 (50%). If the area of the surface of the floating gate near the control gate is increased by 100%, C1 would increase to 1.0, and CC would increase to 0.67 (67%). With this increase, the size of the gates could be decreased by 50%, which would reduce the coupling coefficient by 17% back to the original 50%. As can be determined from the equation, the coupling coefficient can never reach the ideal state (1.00) since the capacitance between the floating gate and the control gate is always divided by itself plus some additional capacitance. Still, the goal of designers is to bring the coupling coefficient as close to unity as possible.
A structure used with dynamic random access memories (DRAMs) to increase the available storage area is a container cell. For example, U.S. Pat. No. 5,354,705 by Mathews et al., assigned to Micron Technology, Inc. and incorporated herein by reference in its entirety, describes a DRAM container cell and method of manufacture. The container cell, which is in direct electrical contact with the semiconductor wafer, often through a silicide layer, increases the surface area on which electrons can be stored. Mathews also describes the use of textured polysilicon, which further increases the surface area of the storage node cell plate and augments the charge that can be stored on the node. Using a textured capacitor storage node allows a decrease in the size of the DRAM, and therefore an increase in the density of the DRAM, while maintaining an equal capacitance. The use of textured polysilicon has been described with applications to floating gate devices, for example in U.S. Pat. No. 5,089,867 by Roger Lee, assigned to Micron Technology, Inc. and incorporated herein by reference in its entirety. Lee describes a floating gate having a textured upper surface which increases the coupling between the floating and control gates.
A method and structure for use with a floating gate device which increases the coupling coefficient between the floating and control gates would be desirable.
The present invention provides a new structure and method for forming the structure which increases coupling between the floating gate and the control gate. In accordance with one embodiment of the invention, a floating gate memory device comprises a first polysilicon floating gate layer oriented in a first direction and a second polysilicon floating gate layer oriented predominantly in a second direction generally perpendicular with the first direction. The second layer electrically contacts the first layer and has a portion which defines a recess therein. The second layer has a larger and predominantly vertically oriented surface area in comparison to a conventional cell, and thus the cell requires no additional horizontal space. The recess receives a control gate layer which has a surface conformal and substantially coextensive with the second floating gate layer, and thus the coupling coefficient between the floating gate and the control gate is increased.
Increasing the coupling between the floating and control gates increases the coupling coefficient of the transistor if the line width (and cell size) is maintained, or allows for a decrease in the line with (and cell size) while maintaining the coupling coefficient of the transistor.
Objects and advantages will become apparent to those skilled in the art from the following detailed description read in conjunction with the appended claims and the drawings attached hereto.